1. Field of the Invention
The invention relates to timing controllers for a liquid crystal display (LCD), and more particularly to timing controllers adjusting the driving strength of an output buffer.
2. Description of the Related Art
Generally, a liquid crystal display (LCD), which includes two panels with respective polarizers and a liquid crystal layer with dielectric anisotropy disposed therebetween, displays desired images by application of electric field to the liquid crystal layer to control the amount of light passing through the panels. The LCD includes a plurality of pixels arranged in a matrix, a plurality of gate lines transmitting gate signals to the pixels and extending in a row direction, and a plurality of data lines transmitting data signals to the pixels and extending in a column direction. Each pixel includes a liquid crystal capacitor and a switching element connected thereto, and the liquid crystal capacitor has a pixel electrode and a reference electrode generating electric field in cooperation and a liquid crystal layer interposed therebetween. Each switching element is connected to one gate line and one data line to be turned on or turned off in response to the gate signal, thereby transmitting the data signal to the pixel electrode. The magnitude of the electric field applied to the liquid crystal layer depends on the difference between the voltage of a reference signal (hereinafter, referred to as a reference voltage) applied to the reference electrode and the voltage of the data signal (hereinafter, referred to as a data voltage). The reference electrode and the pixel electrode may be formed on the same panel or different panels.
When gate-on voltages are sequentially applied to the gate lines, the switching elements connected thereto are turned on. At the same time, the data lines connected to the turned-on switching elements are applied with appropriate data voltages, which are applied to the respective pixel electrodes in a pixel row via the turned-on switching elements. In this manner, the gate-on voltages are applied to all the gate lines to supply the data voltages to the pixels in all the rows, such a cycle being referred to as a frame.
The timing controller is supplied from an external graphic controller with RGB color signals and timing signals controlling the display thereof, for example, vertical synchronizing signals, horizontal synchronizing signals, a clock signal, a data enable signal, etc. In response to the timing signals, the timing controller sends gate control signals to the gate driver, and the RGB color signals and data control signals to the source driver.
To avoid signal attenuation, the conventional timing controller outputs driving signals such that the gate control signals, clock and the RGB color signals have a fixed driving strength according to the loading of the circuit to be driven. However, the driving strength designed for the driving signals with high frequency may not be applicable with that of low frequency. For example, the optimum driving strength selected for the driving signal with low frequency may not enough for that with high frequency. Similarly, the optimum driving strength selected for the driving signal with high frequency may cause problems of overshoot, crosstalk, and even electromagnetic interference when applied to that with low frequency.